知识与财富的链接
提出一种可以表征STI型LDMOS器件各个区域界面陷阱密度分布的测试方法——MR-DCIV,利用该方法得到包括LDMOS器件的沟道区、积累区和漂移区在内的LDMOS器件界面陷阱密度在多种热载流子应力条件下的产生退化规律。针对界面陷阱的位置对LDMOS器件电学特性的影响进行分析,结果显示,在最大衬底电流应力模式下,产生的导通电阻退化最为严重,从而揭示不同于传统MOSFET器件导致LDMOS器件热载流子退化的机理。
A multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation from the channel to STI drift region. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by MR-DCIV technique. The impact of interface state location on device electrical characteristics is analyzed. The result reveals that the maximum Isub stress becomes the worst degradation mode in term of the on-resistance degradation, and the dominant degradation mechanism under hot-carrier stress is different from the conventional MOSFETs.